If a large amount of information is to be stored in a semiconductor memory device, the capacitance of a capacitor of a memory cell in the semiconductor memory device has to be increased per unit area.
Conventionally, in order to increase the capacitance per unit area, a FIN or cylindrical electrode was formed to increase the surface area of the storage electrode of the capacitor.
In this conventional method, however, the process for forming the FIN or cylindrical storage electrode becomes very complicated as the density of the DRAM cells increases. Consequently, various problems have arisen.
FIGS. 1A-1F illustrate a conventional method of forming a capacitor for a semiconductor device. The conventional method and the accompanying problems will be described referring to FIGS. 1A-1F.
First, as shown in FIG. 1A, an oxide layer or a nitride layer is deposited upon a substrate 11 having an impurity diffusion region 16. Then, an insulating layer 12 is formed thereon for insulating the substrate 11 from a conductive layer to be formed later.
Then, a mask pattern 17-1 is formed on the insulating layer 12 and then, utilizing the mask pattern 17-1, a portion of the insulating layer 12 which is formed above the impurity diffusion region 16 is etched, thereby forming a contact hole 18. This contact hole 18 is for electrically connecting the impurity diffusion region 16 to a storage electrode (node electrode) which is to be formed later.
Then, as shown in FIG. 1B, in order to form a storage electrode of the capacitor, a conductive layer 14 is formed within the contact hole 18 and on the insulating layer 12 using polysilicon.
Then, an oxide layer is formed upon the conductive layer 14 and then, a second mask pattern 17-2 is formed. Then, using the second mask pattern 17-2, the oxide layer is etched to form an oxide layer cylinder 13. This oxide layer cylinder 13 serves later as a support for forming an inner cylinder of a cylindrical storage electrode.
Then, as shown in FIG. 1C, another conductive layer 14-2 is deposited on the conductive layer 14 and the oxide layer cylinder 13.
Then, as shown in FIG. 1D, another oxide layer is formed on the conductive layer 14-2 and then, this oxide layer is etched back to form an insulating layer side wall 13-2 which is to serve as a support for forming an outer cylinder of a multi-layer cylinder.
Then, as shown in FIG. 1E, another conductive layer 14-3 is deposited and then, etching is carried out on the conductive layers to form three conductive layers 14-1, 14-2 and 14-3, such that the top of the insulating layer cylinder 13 is exposed.
Then, as shown in FIG. 1F, the oxide layer cylinder 13 and the insulating layer side wall 13-2 are removed, thereby forming a storage electrode 15-1 of the capacitor.
Then, a dielectric layer 15-2 is formed on the surface of the storage electrode 15-1 and then, polysilicon is deposited to form a plate electrode 15-3, thereby completing the formation of the capacitor.
In the conventional capacitor formed as described above, the height of the storage electrode 15-1 is formed such that the outer cylinder of the storage electrode 15-1 is smaller than the inner cylinder of the storage electrode 15-1.
Furthermore, sharp portions are formed on the leading ends of the cylinders. When the memory device is actually used, the electric field concentrates on these sharp portions of the cylinders. As a result, leakage current is increased and the reliability of the memory device is aggravated.
Moreover, when a multi-layer cylinder capacitor is manufactured, two mask processes are required which complicates the formation process.